rtl/verilog/tracer.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Trace logger                                                ////
   4 ////                                                              ////
   5 ////  Description                                                 ////
   6 ////                                                              ////
   7 ////  Logs the signals 'trig0', 'data0', data1, ...               ////
   8 ////  after a trigger event has occurred.                         ////
   9 ////                                                              ////
  10 ////  WB interface:                                               ////
  11 ////  Write Address 0x0000, Arm the trigger                       ////
  12 ////  Read Address  0x0000 - 0x03ff, Read trig0 trace log         ////
  13 ////  Read Address  0x0400 - 0x07ff, Read data0 trace log         ////
  14 ////  Read Address  0x0800 - 0x0bff, Read data1 trace log         ////
  15 ////  Read Address  0x0C00 - 0x0fff, Read data2 trace log         ////
  16 ////                                                              ////
  17 ////  Author(s):                                                  ////
  18 ////    - Stefan Kristiansson, stefan.kristiansson@saunalahti.fi  ////
  19 ////                                                              ////
  20 //////////////////////////////////////////////////////////////////////
  21 ////                                                              ////
  22 //// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
  23 ////                                                              ////
  24 //// This source file may be used and distributed without         ////
  25 //// restriction provided that this copyright statement is not    ////
  26 //// removed from the file and that any derivative work contains  ////
  27 //// the original copyright notice and the associated disclaimer. ////
  28 ////                                                              ////
  29 //// This source file is free software; you can redistribute it   ////
  30 //// and/or modify it under the terms of the GNU Lesser General   ////
  31 //// Public License as published by the Free Software Foundation; ////
  32 //// either version 2.1 of the License, or (at your option) any   ////
  33 //// later version.                                               ////
  34 ////                                                              ////
  35 //// This source is distributed in the hope that it will be       ////
  36 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  37 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  38 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  39 //// details.                                                     ////
  40 ////                                                              ////
  41 //// You should have received a copy of the GNU Lesser General    ////
  42 //// Public License along with this source; if not, download it   ////
  43 //// from http://www.opencores.org/lgpl.shtml                     ////
  44 ////                                                              ////
  45 //////////////////////////////////////////////////////////////////////
  46 `timescale 1ns / 1ps
  47
  48 module tracer(
  49     // WB
  50     input  wire        wb_rst_i,
  51     input  wire        wb_clk_i,
  52     input  wire [31:0] wb_dat_i,
  53     input  wire [13:2] wb_adr_i,
  54     input  wire [3:0]  wb_sel_i,
  55     input  wire        wb_we_i,
  56     input  wire        wb_cyc_i,
  57     input  wire        wb_stb_i,
  58     output wire [31:0] wb_dat_o,
  59     output reg         wb_ack_o,
  60     output wire        wb_err_o,
  61     output wire        wb_rty_o,
  62
  63     // Tracer signals
  64     input wire [31:0]  trig0_i,
  65     input wire [31:0]  data0_i,
  66     input wire [31:0]  data1_i,
  67     input wire [31:0]  data2_i
  68 );
  69     //--------------------------------------------------------------------------
  70     // Wishbone
  71     //--------------------------------------------------------------------------
  72     reg  [31:0] trigger;
  73     reg  [31:0] trig0_rd;
  74     reg  [31:0] data0_rd;
  75     reg  [31:0] data1_rd;
  76     reg  [31:0] data2_rd;
  77     reg         new_trig;
  78     // Read
  79     assign wb_dat_o = (wb_adr_i[13:12] == 2'b00) ? trig0_rd :
  80                       (wb_adr_i[13:12] == 2'b01) ? data0_rd :
  81                       (wb_adr_i[13:12] == 2'b10) ? data1_rd :
  82                       (wb_adr_i[13:12] == 2'b11) ? data2_rd :
  83                       32'b0;
  84
  85     // Write
  86     always @(posedge wb_clk_i) begin
  87       new_trig <= 0;
  88       if (wb_rst_i)
  89         trigger <= 32'h00000000;
  90       else if (wb_stb_i & wb_cyc_i & wb_we_i)
  91         if (wb_adr_i == 0) begin
  92           trigger  <= wb_dat_i;
  93           new_trig <= 1;
  94         end
  95     end
  96
  97     // Ack generation
  98     always @(posedge wb_clk_i)
  99       if (wb_rst_i)
 100         wb_ack_o <= 0;
 101       else if (wb_ack_o)
 102         wb_ack_o <= 0;
 103       else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
 104         wb_ack_o <= 1;
 105
 106     assign wb_err_o = 0;
 107     assign wb_rty_o = 0;
 108
 109
 110     //--------------------------------------------------------------------------
 111     // Trigger
 112     //--------------------------------------------------------------------------
 113     reg [11:2] mem_pos;
 114     reg        running;
 115     reg        done;
 116
 117     always @(posedge wb_clk_i)
 118       if (wb_rst_i | new_trig)
 119         running <= 0;
 120       else if (trig0_i == trigger)
 121         running <= 1;
 122
 123     always @(posedge wb_clk_i)
 124       if (wb_rst_i | new_trig)
 125         mem_pos <= 0;
 126       else if (running & !(&mem_pos))
 127         mem_pos <= mem_pos + 1;
 128
 129     always @(posedge wb_clk_i)
 130       if (wb_rst_i | new_trig)
 131         done <= 0;
 132       else if (&mem_pos)
 133         done <= 1;
 134
 135
 136     //--------------------------------------------------------------------------
 137     // Logging logic (Block RAM's)
 138     //--------------------------------------------------------------------------
 139     reg  [31:0] trig0_mem[1023:0];
 140     reg  [31:0] data0_mem[1023:0];
 141     reg  [31:0] data1_mem[1023:0];
 142     reg  [31:0] data2_mem[1023:0];
 143     reg  [31:0] trig0_q;
 144     reg  [31:0] data0_q;
 145     reg  [31:0] data1_q;
 146     reg  [31:0] data2_q;
 147     wire        wr_en;
 148     wire [11:2] wr_addr;
 149
 150     assign wr_addr = mem_pos;
 151     assign wr_en   = running & !done;
 152
 153     always @(posedge wb_clk_i) begin
 154       trig0_q <= trig0_i;
 155       data0_q <= data0_i;
 156       data1_q <= data1_i;
 157       data2_q <= data2_i;
 158     end
 159
 160     always @(posedge wb_clk_i) begin
 161       if (wr_en) begin
 162         trig0_mem[wr_addr] <= trig0_q;
 163         data0_mem[wr_addr] <= data0_q;
 164         data1_mem[wr_addr] <= data1_q;
 165         data2_mem[wr_addr] <= data2_q;
 166       end
 167       trig0_rd <= trig0_mem[wb_adr_i[11:2]];
 168       data0_rd <= data0_mem[wb_adr_i[11:2]];
 169       data1_rd <= data1_mem[wb_adr_i[11:2]];
 170       data2_rd <= data2_mem[wb_adr_i[11:2]];
 171     end
 172 endmodule